The gate level extrinsic evolvable hardware (EHW) approach to synthesize the sequential logic is proposed in first time. EHW approach is based on the idea of combining reconfiguration hardware device with genetic algorithm to execute reconfiguration autonomously. The problem of interest is to design a sequential circuit that perform a desired function specified by truth table. In this case a set of available logic gates is given in advance. A proposed approach extends to sequential logic design the gate- and function-level extrinsic EHW discussed in [reference: EuroGP'2000]. Since sequential logic circuits have feed-back connection, a new chromosome representation has to be introduced. As a consequence, new genetic operators have to be defined. Evaluation of obtained solution is performed using truth table. The simulated evolution is used to synthesize a circuit using convention method.